NXP Semiconductors /QN908XC /SYSCON /XTAL_CTRL

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Interpret as XTAL_CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (XTAL_XCUR_BOOST_REG)XTAL_XCUR_BOOST_REG 0 (XTAL_BPXDLY)XTAL_BPXDLY 0 (XTAL_BP_HYSRES_REG)XTAL_BP_HYSRES_REG 0 (XTAL_XSMT_EN_REG)XTAL_XSMT_EN_REG 0 (XTAL_XRDY_REG)XTAL_XRDY_REG 0 (XTAL_XOUT_DIS_REG)XTAL_XOUT_DIS_REG 0 (DIV_DIFF_CLK_DIG_DIS)DIV_DIFF_CLK_DIG_DIS 0XTAL_SU_CB_REG 0XTAL_SU_CA_REG 0 (XTAL_INV)XTAL_INV 0 (XTAL_DIV)XTAL_DIV

Description

crystal control register

Fields

XTAL_XCUR_BOOST_REG

1 to increase 16/32 MHz xtal current

XTAL_BPXDLY

Bypass the power up delay in the XTAL core.

XTAL_BP_HYSRES_REG

1 to bypass the degeneration resistor in order to reduce the hysteresis voltage

XTAL_XSMT_EN_REG

1 to use hysteresis buffer

XTAL_XRDY_REG

1 to set xtal ready signal by register

XTAL_XOUT_DIS_REG

1 not to send 16/32 MHz xtal clk out

DIV_DIFF_CLK_DIG_DIS

disable differential clock of digital

XTAL_SU_CB_REG

Register controlled load cap of the XTAL_B in speed up modeCB=2pF+0.35pFSU_CB+5pFXADD_C

XTAL_SU_CA_REG

Register controlled load cap of the XTAL_A in speed up modeCA=2pF+0.35pFSU_CA+5pFXADD_C

XTAL_INV

Inverse crystal clock

XTAL_DIV

Divide crystal clock when external crystal is 32M this bit should be configured into 1 otherwise 0.

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